A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits

A Digital Metastability Model for VLSI Circuits

PhD Thesis A Digital Metastability Model for VLSI Circuits PhD candidate Thomas Polzer Reviewers Ao. Univ.-Prof. Dipl.-Ing. Dr. techn. Andreas Steininger Prof. Alex Yakovlev, PhD, DSc This thesis develops a digital model for predicting failure rates caused by marginal triggering, so called metastability, of CMOS storage elements. To derive the underlying model, various storage elements are simu...

Digital Circuits Delay Analysis

The speed of digital circuit is one of the most restricting factors in the deep sub-micron and multigigahertz integrated circuits design. It is directly dependent on the circuit delay. Scaling down the technologies and increasing the operational frequency make the delay problems more important. This paper studies the delay in digital circuits, starting from the design process, scaling down the ...

Ground bounce in digital VLSI circuits

Delay Estimation of VLSI Circuits from a High-Level View†

Estimation of the delay of a Boolean function from its functional description is an important step towards design exploration at the register transfer level (RTL). This paper addresses the problem of estimating the delay of certain optimal multi-level implementations of combinational circuits, given only their functional description. The proposed delay model uses a new complexity measure called...

A survey of power estimation techniques in VLSI circuits

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and e cient power estimation during the design phase is required in order to meet the power speci cations without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniqu...